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| CY28301 Frequency Generator for Intel(r) Integrated Chipset Features * Single chip FTG solution for Intel Solano/810E/810 * Support SMBus byte Read/Write and block Read/Write operations to simplify system BIOS development * Vendor ID and revision ID support * Maximized EMI suppression using Cypress's Spread Spectrum technology * Low jitter and tightly controlled clock skew * Two copies of CPU clock * Thirteen copies of SDRAM clock * Eight copies of PCI clock * One copy of synchronous APIC clock * Three copies of 66 MHz outputs * Two copies of 48 MHz outputs * One copy of 14.31818 MHz reference clock (R) Key Specifications CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps APIC, 48 MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter: ................................................... 500 ps CPU, 3V66 Output Skew:............................................ 175 ps SDRAM, APIC, 48-MHz Output Skew:........................ 250 ps PCI Output Skew:........................................................ 500 ps CPU to SDRAM Skew (@ 133 MHz) ......................... 0.5 ns CPU to SDRAM Skew (@ 100 MHz)..................4.5 to 5.5 ns CPU to 3V66 Skew (@ 66 MHz) ........................7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead)...........................1.5 to 3.5 ns PCI to APIC Skew ...................................................... 0.5 ns Block Diagram VDD_REF REF/FS1 Pin Configuration[1] X1 X2 XTAL OSC PLL REF FREQ SDATA SCLK SMBus Logic Divider, Delay, and Phase Control Logic (FS0:4) PLL 1 PD# PLL2 /2 VDD_REF X1 X2 GND_REF VDD_CPU GND_3V66 3V66_0 CPU0:1 3V66_1 2 3V66_2 VDD_3V66 VDD_APIC VDD_PCI APIC PCI0 PCI1 VDD_3V66 PCI2/SEL24_48MHz#* 3V66_0:2 GND_PCI 3 VDD_PCI PCI3 PCI4 PCI0 PCI5 PCI1 VDD_PCI PCI2/SEL24_48MHz#* PCI6 PCI3:7 5 PCI7 GND_PCI VDD_SDRAM PD#* SDRAM0:11, SCLK 13 SDRAM_F SDATA VDD_SDRAM SDRAM11 SDRAM10 VDD_48MHz GND_SDRAM 48MHz/FS0 24_48MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF/FS1* VDD_APIC APIC VDD_CPU CPU0 CPU1 GND_CPU GND_SDRAM SDRAM0 SDRAM1 SDRAM2 VDD_SDRAM SDRAM3 SDRAM4 SDRAM5 GND_SDRAM SDRAM6 SDRAM7 SDRAM_F VDD_SDRAM GND_48MHz 24_48MHz 48MHz/FS0* VDD_48MHz VDD_SDRAM SDRAM8 SDRAM9 GND_SDRAM Note: 1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH. CY28301 Rev 1.0, November 27, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 13 www.SpectraLinear.com CY28301 Pin Definitions Pin Name REF/FS1 Pin No. 56 Pin Type I/O Pin Description Reference Clock /Frequency Select 1: 3.3V 14.318-MHz clock output. This pin also serves as the select strap to determine the device operating frequency (as described in Table 5). Crystal Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Output: An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected. PCI Clock 0: 3.3V 33-MHz PCI clock output. PCI Clock 1: 3.3V 33-MHz PCI clock output. PCI Clock 2/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine the output frequency for 24_48MHz output. Logic 1 = 24 MHz on pin 35. PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually turned off via the SMBus interface. 66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled by FS0:1 (see Table 5). 48-MHz Output/Frequency Selection 1: 3.3V 48-MHz non-spread spectrum output. This pin also serves as the select strap to determine the device operating frequency (as described in Table 5.) 24- or 48-MHz Output: 3.3V 24- or 48-MHz non-spread spectrum output. Power-down Input: LVTTL-compatible asynchronous input that places the device in power-down mode when held LOW. CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies depending on the configuration of FS0:1. Voltage swing is set by VDDQ2. SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The operating frequency is controlled by FS0:1 (see Table 5). X1 2 I X2 3 O PCI0 PCI1 PCI2/SEL24_48MHz# 11 12 13 O O O PCI3:7 3V66_0:2 48MHz/FS0 15, 16, 17, 19, 20 6, 7, 8 34 O O I/O 24_48MHz PD# CPU0:1 35 22 52, 51 O I O SDRAM0:11, SDRAM_F 48, 47, 46, 44, 43, 42, 40, 39, 31, 30, 27, 26, 38 54 24 23 1, 9, 10, 18, 25, 32, 37, 45, 33 O APIC SDATA SCLK VDD_REF, VDD_3V66, VDD_PCI, VDD_SDRAM, VDD_48MHz VDD_CPU, VDD_APIC GND_REF, GND_3V66, GND_PCI, GND_SDRAM, GND_48MHZ, GND_CPU O I/O I P Synchronous APIC Clock Outputs: Clock outputs running synchronous with the PCI clock outputs. Voltage swing set by VDDQ2. Data pin for SMBus circuitry. Clock pin for SMBus circuitry. 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, reference output buffers, and 48-MHz output buffers. Connect to 3.3V. 2.5V Power Connection: Power supply for APIC and CPU output buffers. Connect to 2.5V. Ground Connections: Connect all ground pins to the common system ground plane. 53, 55 4, 5, 14, 21, 28, 29, 41, 49, 50, 36 P G Rev 1.0, November 27, 2006 Page 2 of 13 CY28301 Serial Data Interface The CY28301 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word Write, byte/word Read, block Write, and block Read operations from Table 1. Command Code Definition Bit 7 6:0 Descriptions 0 = Block Read or block Write operation 1 = Byte/Word Read or byte/word Write operation Byte offset for byte/word Read or Write operation. For block Read or Write operations, these bits need to be set at `0000000.' the controller. For block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. For byte/word Write and byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code. The definition for the command code is defined as follows. Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 ... ... ... ... Start Slave address - 7 bits Write Acknowledge from slave Command code - 8-bits `00000000' stands for block operation Acknowledge from slave Byte count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte N/Slave acknowledge... Data byte N - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 ... ... ... ... Start Slave address - 7 bits Write Acknowledge from slave Command code - 8 bits `00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave -8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/acknowledge Data byte N from slave - 8 bits Not acknowledge Stop Block Read Protocol Description Rev 1.0, November 27, 2006 Page 3 of 13 CY28301 Table 3. Word Read and Word Write Protocol Word Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bits `1xxxxxxx' stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte low - 8 bits Acknowledge from slave Data byte high - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command code - 8 bits `1xxxxxxx' stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte low from slave - 8 bits Acknowledge Data byte high from slave - 8 bits Not acknowledge Stop Word Read Protocol Description 19 20:27 28 29:36 37 38 19 20 21:27 28 29 30:37 38 39:46 47 48 Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command code 8 - bits `1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte 8 - bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write Acknowledge from slave Command code - 8 bits `1xxxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop Byte Read Protocol Description 19 20:27 28 29 19 20 21:27 28 29 30:37 38 39 Rev 1.0, November 27, 2006 Page 4 of 13 CY28301 CY28301 Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 2. All unused register bits (reserved and N/A) should be written to a "0" level. 3. All register bits labeled "Initialize to 0" must be written to "0" during initialization. Byte 0: Control Register 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# - - - - - - - - SEL1 SEL0 Reserved Reserved FS_Override Spread Select2 Spread Select1 Spread Select0 Name Default 0 0 0 0 0 0 0 0 See 5 See 5 Reserved Reserved 0 = Select operating frequency by FS[1:0] input pins 1 = Select operating frequency by SEL[1:0] settings `000' = Normal (spread off) `001' = Test mode `010' = Reserved `011' = Three-stated `100' = -0.5% `101' = -0.75% `110' = -1.0% `111' = -0.3% Byte 1: Control Register 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 56 34 - - - - 56 56 Name Latched FS1 input Latched FS0 input Reserved Reserved Reserved Reserved REF REF_DRV Default X X 0 0 0 0 1 0 Reserved Reserved Reserved Reserved (Active/Inactive) REF Clock output drive strength 0 = Normal 1= High drive Description Latched FS[1:0] inputs. These bits are Read-only. Description Rev 1.0, November 27, 2006 Page 5 of 13 CY28301 Byte 2: Control Register 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3: Control Register 3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 4: Control Register 4 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 5: Control Register 5 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# - - - 38 26 27 30 31 Name Reserved Reserved Reserved SDRAM_F SDRAM11 SDRAM10 SDRAM9 SDRAM8 Default 0 0 0 1 1 1 1 1 Reserved Reserved Reserved (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Description Pin# 39 40 42 43 44 46 47 48 Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Default 1 1 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Description Pin# 8 7 6 54 - - 51 52 Name 3V66_2 3V66_1 3V66_0 APIC Reserved Reserved CPU1 CPU0 Default 1 1 1 1 0 0 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Reserved Reserved (Active/Inactive) (Active/Inactive) Description Pin# 20 19 17 16 15 13 12 11 PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Name Default 1 1 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Description Byte 6: Vendor ID and Revision ID Register (Read-only) Bit Bit 7 Bit 6 Name Revision_ID3 Revision_ID2 Default 0 0 Revision ID bit[3] Revision ID bit[2] Pin Description Rev 1.0, November 27, 2006 Page 6 of 13 CY28301 Byte 6: Vendor ID and Revision ID Register (Read-only) Bit Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Revision_ID1 Revision_ID0 Vendor_ID3 Vendor_ID2 Vendor _ID1 Vendor _ID0 Default 0 0 1 0 0 0 Revision ID bit[1] Revision ID bit[0] Bit[3] of Cypress's Vendor ID. This bit is Read-only. Bit[2] of Cypress's Vendor ID. This bit is Read-only. Bit[1] of Cypress's Vendor ID. This bit is Read-only. Bit[0] of Cypress's Vendor ID. This bit is Read-only. Pin Description Byte 7: Control Register 7 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 8: Reserved Register Bit Bit 7 Bit 6 Name PCI_Skew1 PCI_Skew0 Default 0 0 PCI skew control 00 = Normal 01 = -500 ps 10 = Reserved 11 = +500 ps Reserved. Write with `1' Reserved. Write with `1' Reserved. Write with `1' Reserved. Write with `1' Reserved. Write with `1' Reserved Pin Description Pin# - 35 34 - 35 34 - - Name Reserved 24_48MHz_DRV 48MHz_DRV Reserved 24_48MHz 48 MHz Reserved Reserved Default 0 1 1 0 1 1 0 0 Reserved 0 = Norm, 1 = High drive 0 = Norm, 1 = High drive Reserved (Active/Inactive) (Active/Inactive) Reserved Reserved Pin Description Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Reserved Reserved Reserved Reserved Reserved 1 1 1 1 1 0 Byte 9: Reserved Register Bit Bit 7 Name SDRAM_DRV Default 0 Pin Description SDRAM clock output drive strength 0 = Normal 1 = High Drive PCI and AGP clock output drive strength 0 = Normal 1 = High drive Reserved Reserved Reserved Reserved Reserved Reserved Bit 6 PCI_DRV 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 Rev 1.0, November 27, 2006 Page 7 of 13 CY28301 Byte 10: Reserved Register Bit Bit 7 Bit 6 Bit 5 Name CPU_Skew2 CPU_Skew1 CPU_Skew0 Default 0 0 0 CPU skew control 000 = Normal 001 = -150 ps 010 = -300 ps 011 = -450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps SDRAM skew control 000 = Normal 001 = -150 ps 010 = -300 ps 011 = -450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps AGP skew control 00 = Normal 01 = -150 ps 10 = +150 ps 11 = +300 ps Description Bit 4 Bit 3 Bit 2 SDRAM_Skew2 SDRAM_Skew1 SDRAM_Skew0 0 0 0 Bit 1 Bit 0 AGP_Skew1 AGP_Skew0 0 0 Byte 11: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Byte 12: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Byte 13: Reserved Register Bit Bit 7 Bit 6 Bit 5 Name Reserved Reserved Reserved Default 0 0 0 Reserved Reserved Reserved Pin Description Rev 1.0, November 27, 2006 Page 8 of 13 CY28301 Byte 13: Reserved Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Byte 14: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Byte 15: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 16: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Byte 17: Reserved Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Pin# - - - - - - - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Pin# - - - - - - - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Pin# - - - - - - - - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved. Write with `1' Reserved. Write with `1' Description Rev 1.0, November 27, 2006 Page 9 of 13 CY28301 Table 5. Frequency Selections through HW Strap Option and Serial Data Interface Data Bytes Input Conditions FS1 SEL1 0 0 1 1 FS0 SEL0 0 1 0 1 CPU 66.6 100.0 133.3 133.3 SDRAM 100.0 100.0 133.3 100.0 3V66 66.6 66.6 66.6 66.6 PCI 33.3 33.3 33.3 33.3 APIC 16.6 16.6 16.6 16.6 Output Frequency DC Electrical Characteristics[2] DC parameters must be sustainable under steady state (DC) conditions. Absolute Maximum DC Power Supply Parameter VDDQ3 VDDQ2 TS Description 3.3V Core Supply Voltage 2.5V I/O Supply Voltage Storage Temperature Min. -0.5 -0.5 -65 Max. 4.6 3.6 150 Unit V V C Absolute Maximum DC I/O Parameter Vi/o3 Vi/o3 ESD prot. Description 3.3V Core Supply Voltage 2.5V I/O Supply Voltage Input ESD Protection Min. -0.5 -0.5 2000 Max. 4.6 3.6 Unit V V V DC Operating Requirements Parameter VDD3 VDDQ3 VDDQ2 VDD3 = 3.3V 5% Vih3 Vil3 Iil VDDQ2 = 2.5V 5% Voh2 Vol2 VDDQ3 = 3.3V 5% Voh3 Vol3 VDDQ3 = 3.3V 5% Vpoh3 Vpol3 PCI Bus Output High Voltage PCI Bus Output Low Voltage Ioh = (-1 mA) Iol = (1 mA) 2.4 0.55 V V 3.3V Output High Voltage 3.3V Output Low Voltage Ioh = (-1 mA) Iol = (1 mA) .4 0.4 V V 2.5V Output High Voltage 2.5V Output Low Voltage Ioh = (-1 mA) Iol = (1 mA) 2.0 0.4 V V 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current[3] 0 < Vin Rev 1.0, November 27, 2006 Page 10 of 13 CY28301 DC Operating Requirements (continued) Parameter Cin Cxtal Cout Lpin Ta Description Input Pin Capacitance Xtal Pin Capacitance Output Pin Capacitance Pin Inductance Ambient Temperature No airflow 0 0 13.5 Condition Min. Max. 5 22.5 6 7 70 Unit pF pF pF nH C AC Electrical Characteristics[2] (TA = 0C to +70C, VDDQ3 = 3.3V 5%, VDDQ2= 2.5V 5% fXTL = 14.31818 MHz) 66.6-MHz Host Parameter CPUCLK TPeriod THIGH TLOW TRISE TFALL SDRAM TPeriod THIGH TLOW TRISE TFALL APIC TPeriod THIGH TLOW TRISE TFALL 3V66 TPeriod THIGH TLOW TRISE TFALL Description Host/CPUCLK Period Host/CPUCLK High Time Host/CPUCLK Low Time Host/CPUCLK Rise Time Host/CPUCLK Fall Time SDRAM CLK Period SDRAM CLK High Time SDRAM CLK Low Time SDRAM CLK Rise Time SDRAM CLK Fall Time APIC CLK Period APIC CLK High Time APIC CLK Low Time APIC CLK Rise Time APIC CLK Fall Time 3V66 CLK Period 3V66 CLK High Time 3V66 CLK Low Time 3V66 CLK Rise Time 3V66 CLK Fall Time Min. 15.0 5.2 5.0 0.4 0.4 10.0 3.0 2.8 0.4 0.4 60.0 25.5 25.3 0.4 0.4 15.0 5.25 5.05 0.5 0.5 Max. 15.5 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 64.0 N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 100-MHz Host Min. 10.0 3.0 2.8 0.4 0.4 10.0 3.0 2.8 0.4 0.4 60.0 25.5 25.30 0.4 0.4 15.0 5.25 5.05 0.5 0.5 Max. 10.5 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 N/A N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 133-MHz Host Min. 7.5 1.87 1.67 0.4 0.4 10.0 3.0 2.8 0.4 0.4 60.0 25.5 25.30 0.4 0.4 15.0 5.25 5.05 0.5 0.5 Max. 8.0 N/A N/A 1.6 1.6 10.5 N/A N/A 1.6 1.6 64.0 N/A N/A 1.6 1.6 16.0 N/A N/A 2.0 2.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 8 5 6 4 5 6 4 5 6 Notes 4 5 6 Notes: 4. Period, jitter, offset, and skew measured on the rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks. 5. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and operating within specifications. 6. TRISE and TFALL are measured as transitions through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification. 7. THIGH is measured at 2.0V for 2.5V outputs, and 2.4V for 3.3V outputs. 8. TLOW is measured at 0.4V for all outputs. Rev 1.0, November 27, 2006 Page 11 of 13 CY28301 AC Electrical Characteristics[2] (TA = 0C to +70C, VDDQ3 = 3.3V 5%, VDDQ2= 2.5V 5% fXTL = 14.31818 MHz) 66.6-MHz Host Parameter PCI TPeriod THIGH TLOW TRISE TFALL tpZL, tpZH tpLZ, tpZH tstable Description PCI CLK Period PCI CLK High Time PCI CLK Low Time PCI CLK Rise Time PCI CLK Fall Time Output Enable Delay (All outputs) Output Disable Delay (All outputs) All Clock Stabilization from Power-Up Min. 30.0 12.0 12.0 0.5 0.5 1.0 1.0 Max. N/A N/A N/A 2.0 2.0 10.0 10.0 3 100-MHz Host Min. 30.0 12.0 12.0 0.5 0.5 1.0 1.0 Max. N/A N/A N/A 2.0 2.0 10.0 10.0 3 133-MHz Host Min. 30.0 12.0 12.0 0.5 0.5 1.0 1.0 Max. N/A N/A N/A 2.0 2.0 10.0 10.0 3 Unit ns ns ns ns ns ns ns ms Notes 4, 7 5 6 Group Skew and Jitter Limits Output Group CPU SDRAM APIC 48MHz 3V66 PCI REF Pin-Pin Skew Max. 175 ps 250 ps 250 ps 250 ps 175 ps 500 ps N/A Cycle-Cycle Jitter 250 ps 250 ps 500 ps 500 ps 500 ps 500 ps 1000 ps Output Buffer Clock Output Wave Duty Cycle 45/55 45/55 45/55 45/55 45/55 45/55 45/55 Test Point Nom. VDD 2.5V 3.3V 2.5V 3.3V 3.3V 3.3V 3.3V Skew, Jitter Measure Point 1.25V 1.5V 1.25V 1.5V 1.5V 1.5V 1.5V Test Load TPERIOD Duty Cycle THIGH 2.0 2.5V Clocking Interface 1.25 0.4 TLOW TRISE TFALL TPERIOD Duty Cycle THIGH 2.4 3.3V Clocking Interface 1.5 0.4 TLOW TRISE TFALL Figure 1. Output Buffer Rev 1.0, November 27, 2006 Page 12 of 13 CY28301 Ordering Information Ordering Code CY28301PVC CY28301PVCT Package Type 56-pin SSOP (300 mils) 56-pin SSOP (300 mils) - Tape and Reel Operating Range Commercial, 0C to 70C Commercial, 0C to 70C Package Drawing and Dimension 56-Lead Shrunk Small Outline Package O56 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 27, 2006 Page 13 of 13 |
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